Circuitized substrates such as printed circuit boards (hereinafter also referred to as PCBs), chip carriers, and the like are typically constructed in laminate form in which several layers of dielectric material and conductive material (laminates) are bonded together using relatively high temperature and pressure lamination processes. The conductive layers, typically of thin copper, are usually used in the formed substrate for providing electrical connections to and among various devices located on the surface of the substrate. Examples of such devices are integrated circuits (semiconductor chips) and discrete passive devices, such as capacitors, resistors, inductors, and the like. Discrete passive devices occupy a high percentage of the surface area of the completed substrate, which is undesirable because of the increased demand for miniaturization of products. In order to increase the available substrate surface area, multiple functions can be provided on a single component for mounting on a board. When passive devices are in such a configuration, these are often referred to as integral passive devices; the functions are integrated into the singular component. Because of such external positioning, however, these components still utilize, albeit less than if in singular form, valuable board real estate. In response, there have also been efforts to embed discrete passive components within the board.
A capacitor designed for disposition within a PCB substrate may thus be referred to as an embedded integral passive component or, more simply, an embedded capacitor. Such a capacitor provides internal capacitance. The result of this internal positioning is that it is unnecessary to also position such devices externally on the PCB's outer surface(s).
With respect to a fixed capacitor area, two known approaches increase the planar capacitance (capacitance/area) of an internal capacitor. In one such approach, higher dielectric constant materials can be used, while in a second, the thickness of the dielectric can be reduced. These constraints are reflected in the following formula for capacitance per area:C/A=Dielectric Constant of Laminate×Dielectric Constant in Vacuum/DielectricThickness where: C is the capacitance and A is the area of the capacitor.
As mentioned above, there have been attempts to provide internal capacitance and other internal conductive structures, components or devices within circuitized substrates such as PCBs, some of these including the use of nano-powders.
The needs of the semiconductor marketplace continue to drive density into semiconductor packages. Traditionally, greater wiring densities have been achieved by reducing the dimensions of vias, lines, and spaces, increasing the number of wiring layers, and utilizing blind and buried vias. However, each of these approaches, for example, those related to drilling and plating of high aspect ratio vias, reduced conductance of narrow circuit lines, and increased cost of fabrication related to additional wiring layers, includes inherent limitations.
PCBs, chip carriers and related products used in many of today's technologies must include multiple circuits in a minimum volume or space. Typically, such products comprise a stack of layers of signal, ground and/or power planes separated from each other by at least one layer of electrically insulating dielectric material. The circuit lines or pads (e.g., those of the signal planes) are often in electrical contact with each other by plated holes passing through the dielectric layers. The plated holes are often referred to as vias if internally located, blind vias if extending a predetermined depth within the board from an external surface, or plated-thru-holes (hereinafter also referred to simply as PTHs) if extending substantially through the board's full thickness. The term thru-hole as used herein is meant to include all three types of such board openings.
Complexity of these products has increased significantly in recent years. PCBs for mainframe computers may have as many as seventy-two layers of circuitry or more, with the complete stack having a thickness of as much as about 0.8 inch (800 mils). These boards are typically designed with three or five mil wide signal lines and twelve mil diameter thru-holes. Increased circuit densification requirements seek to reduce signal lines to a width of two mils or less and thru-hole diameters to two mils or less. Many known commercial procedures, especially those of the nature described herein, are incapable of economically forming these dimensions now desired by the industry. Such processes typically comprise fabrication of separate innerlayer circuits (circuitized layers), which are formed by coating a photosensitive layer or film over the copper layer of a copper clad innerlayer base material. The photosensitive coating is imaged and developed and the exposed copper is etched to form conductor lines. After etching, the photosensitive film is stripped from the copper, leaving the circuit pattern on the surface of the innerlayer base material. This processing is also referred to as photolithographic processing in the PCB art and further description is not deemed necessary.
After the formation of the individual innerlayer circuits, a multilayer stack is formed by preparing a lay-up of core innerlayers, ground planes, power planes, etc., typically separated from each other by a dielectric prepreg comprising a layer of glass (typically fiberglass) cloth impregnated with a partially cured material, typically a B-stage epoxy resin. The top and bottom outer layers of the stack usually comprise copper clad, glass-filled epoxy planar substrates with the copper cladding comprising the exterior surfaces of the stack. The stack is laminated to form a monolithic structure using heat and pressure to fully cure the B-stage resin. The stack so formed typically has metal (usually copper) cladding on both of its exterior surfaces. Exterior circuit layers are formed in the copper cladding using procedures similar to the procedures used to form the innerlayer circuits. A photosensitive film is applied to the copper cladding. The coating is exposed to patterned activating radiation and developed. An etchant is then used to remove copper bared by the development of the photosensitive film. Finally, the remaining photosensitive film is removed to provide the exterior circuit layers.
The aforementioned thru-holes (also often referred to as interconnects) are used in many such substrates to electrically connect individual circuit layers within the structure to each other and to the outer surfaces. The thru-holes typically pass through all or a portion of the stack. Thru-holes are generally formed prior to the formation of circuits on the exterior surfaces by drilling holes through the stack at appropriate locations. Following several pre-treatment steps, the walls of the holes are catalyzed by contact with a plating catalyst and metallized, typically by contact with an electroless or electrolytic copper plating solution to form conductive pathways between circuit layers. Following formation of the conductive thru-holes, exterior circuits, or outerlayers are formed using the procedure described above.
The necessity of developing ever-increasing high speed circuitized substrates for use in many of today's new products has led to the exploration of new materials to extend the electrical and thermal performance limits of the presently available technology. For high-speed applications, it is necessary to have extremely dense conductor circuitry patterning on low dielectric constant insulating material. Prepreg laminates for conventional circuit boards consist of a base reinforcing glass fabric impregnated with a resin, also referred to by some in the industry as FR-4 dielectric material. Epoxy/glass laminates used in some current products typically contain approximately 40% by weight fiberglass and 60% by weight epoxy resin.
What is needed to extend the electrical and thermal performance limits of the presently available technology is a low loss capacitive material that enables the simultaneous function as a low loss insulating dielectric layer or as a capacitive layer that is location specific and implemented when needed while the development of new materials progresses. For even higher-speed and tighter space-restricted applications, it may be necessary to provide the board manufacturer with the intrinsic capability of the combination of low loss capacitive and low loss insulating dielectric material.